The high definition television ("high vision") intends to provide new charms such as forceful and attendant feelings which cannot be obtained by the existing television broadcasting; these charms are given by display of a high definition television image on a large-scale wide screen and digital PCM sound.
As a method for band-compressing a high definition television signal, the MUSE (Multiple Sub-Nyquist Sampling Encoding) system has been proposed by Nippon Hoso Kyokai (NHK) (Y. Ninomiya et al "KOHINI TEREBI NO EISEI 1 CHANNEL DENSO HOSIKI" SINGAKURONSI Vol. J68 - D. No. 4 PP. 647-654 (1985); WATANABE, TAKEHARA "HIVISION ONSEI BASE BAND DENSO YO JUNSHUNJIASSIN DPCM HOSIKI" DENSI-JOHO-TSUSIN GAKKAI (Sho 62 March)).
Referring to the drawings, one example of the conventional audio signal demodulation circuits will be explained.
FIGS. 3, 4 and 5 are a block diagram of the conventional audio signal demodulation circuit, a timing chart thereof and a waveform chart thereof, respectively. In FIG. 3, 31 is a bit de-interleave circuit; 32 is an error correction circuit; 33 is a word de-interleave circuit; 34 is an expansion circuit; 35 is a range detection/error correction circuit; 36 is an interpolation circuit; 37 is an integration circuit; 38 is a synchronous detection circuit; and 39 is a muting circuit.
The operation of the audio signal demodulation circuit thus constructed will be explained with reference to FIGS. 3, 4 and 5.
First, an audio input signal at 1350 kb/s is detected in its synchronization pattern by the synchronous detection circuit 38 to be synchronized. The output (synchronization lock signal) from the synchronous detection circuit 38 is applied to the muting circuit 39 so that it is at a high level when the input is synchronized and at a low level if the input is not synchronized.
Also, the input audio signal is bit-de-interleaved on the transmission side by bit-de-interleave circuit 31. The output from the bit de-interleave circuit 31 is error-corrected by the error correction circuit 32 so that one-error correction two error detection is made in the normal mode and two-error correction three-error detection is made in the intensifying mode. The signal subjected to the two-error detection in the normal mode and the three-error detection in the intensifying mode will be used as an interpolation signal in the interpolation circuit 36.
The output from the error correction circuit 32 is word-de-interleaved on the transmission side by word-de-interleave circuit 33.
The output from the error correction circuit 32 is also detected in its range bits and error-detected by the range detection/error correction circuit 35.
The outputs from the word de-interleave circuit 33 is expanded by the expansion circuit 34 in accordance with the range bits detected by the range detection/error correction circuit 35.
The output from the expansion circuit 34 is subjected to the average value interpolation or the previous value interpolation by the previous sample value in the same channel using an interpolation signal output from the error correction circuit 32; a differential value is produced from the interpolation circuit 36. The differential value output from the interpolation circuit 36 is integrated by the integration circuit 37. If the synchronization lock signal output from the synchronous detection circuit 38 is at a low level owing to synchronization unlock, forcible muting or the like, the output from the muting circuit 39 is extracted as an audio signal at the low level.
The operation of the integration circuit 37 and the muting circuit 39 will be explained in further detail.
Now, it is assumed that the differential signal output from the interpolation circuit 36 has the values as shown in (a) of FIG. 4 (for simplicity of illustration, only the values for the same channel in two or four channels are shown). In (a) of FIG. 4, the abscissa represents time (sample No.) and the ordinate represents the differential signal output from the interpolation circuit 36. For example, the differential signal is 2 at time n and it is 3 at time n+1. The output from the integration circuit 37 is obtained by adding the differential value at the time at issue to the integrated value at the previous sampling time. Now, if the output from the integration circuit 37 is muted at time n+4 by the forcible muting, it is placed in the low level at time n+3 as shown in FIG. 5.
However, in the above arrangement, the audio signal is abruptly removed in the cases where the synchronization has been lost or the forcible muting is done so that noise `puff` will be produced.